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PRELIMINARY
DS2441 1-Cell Li-Ion Battery Manager
www.dalsemi.com
FEATURES
Provides all identification, information, instrumentation and protection functions needed in a lithium-ion battery pack Supports one-cell battery packs Protects cell from: - overvoltage (overcharge) - undervoltage (overdischarge) - overcurrent (charging and discharging) - high temperatures (thermal runaway) Current accumulator tracks remaining battery capacity in 0.5% increments Voltage measurement with 10 mV accuracy Temperature measurement with 2 C accuracy eliminates need for thermistor 32-byte user memory stores battery data 64-bit ROM ID uniquely identifies each battery pack 1-WireTM interface carries all commands and data via a single wire Programmable alarm warns when cell is nearly discharged Programmable I/O pin supports LEDs, vibration motors and other features Operating temperature range: -40 to +85 C C 10kV ESD rating
PIN ASSIGNMENT
PIN DESCRIPTION
GND PIO ISENS VM VDD
CHG DCHG
DQ
Ground Programmable I/O pin Current sense input not used, connect to GND Power supply input (2.4V to 10V) Charge control output Discharge control output Data I/O (1-Wire interface)
DESCRIPTION
The DS2441 1-Cell Li-Ion Battery Manager provides all essential functions for monitoring, protecting and managing one-cell lithium-ion battery packs. The DS2441 constantly measures cell voltage, current, and temperature, and automatically takes action to disable charging and/or discharging of the cell to protect it when undesirable conditions arise. Via its 1-Wire interface, the DS2441 provides the host system access to identification information, status data, configuration and control settings, instrumentation registers, and general purpose data storage. Each DS2441 has a factory-programmed 64-bit ROM ID which allows the host system to verify the authenticity of the battery pack as well as a factory-programmed 16-bit manufacturing ID which can be used to encode assembly location, cell chemistry and other information. A full set of status information in the DS2441 keeps the host informed about protection conditions, remaining capacity and other matters. Configuration and control fields in the device allow the host to disable charging and/or discharging, put the battery pack in a low-power mode, and set various timing parameters. In addition, instrumentation 1 of 29
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registers on the chip present the host with high-accuracy temperature, voltage, and current measurements as well as information on remaining capacity and cycle life. Thirty-two bytes of general purpose memory in the DS2441 are available for storing pack-specific information. When the cell voltage reaches the undervoltage cutoff, the DS2441 automatically enters a low-power mode in which it consumes only 1A of battery current. When a battery charger is applied to the pack, the DS2441 automatically leaves its low-power mode to support charging. A refresh feature in the DS2441 allows even the most severely discharged battery packs to be refreshed and recharged. The DS2441 also features a programmable I/O pin that allows the host system to sense and control other electronics in the pack, such as vibration motors, speakers and LEDs.
DETAILED PIN DESCRIPTION Table 1
Pin 1 2 Symbol GND PIO Description Ground. System voltage reference. Connect this pin to the negative terminal of the cell and to one side of the current sense resistor. Programmable Digital I/O. Use this user-definable pin to control features such as a vibration motor or an LED driver, or to monitor an input signal such as a tamper-sensing circuit. Current Sense Input. The DS2441 measures the voltage between this pin and GND to calculate the current flowing through the external sense resistor. Connect this pin through an RC low-pass filter to the PACK- side of the sense resistor. Voltage Monitor Input. Not used on the DS2441. Connect to GND. Power Supply Input. The DS2441 draws operating power through this pin and uses this pin and the GND pin to monitor the voltage of the cell. Voltage on this pin must be between 2.4V and 10V for proper operation. Charge Control Output. Controls an external p-channel charge protection FET. Open-drain output driver. Discharge Control Output. Controls an external p-channel discharge protection FET. Push-pull output driver. Data Input/Output. 1-Wire data line. Parasite power supply for memory read/write operations. DS2441 power supply in Refresh Mode. Open-drain output driver. Connect this pin to the DATA terminal of the battery pack. In the host system, connect a 5 k pullup from the DATA terminal to the PACK+ terminal.
3
ISENS
4 5
VM VDD
6 7 8
CHG DCHG
DQ
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BLOCK DIAGRAM Figure 1
DQ 1-Wire I/O and 64-bit ROM ID Control Logic VREG PIO
DCHG CHG
VDD
GND
MUX
Voltage A/D Registers
Temp Sensor ISENS Current A/D
32-Byte User Memory
APPLICATION EXAMPLE Figure 2
PACK+ DATA
8 DQ DS2441 7 DCHG 6 ISENS CHG 5 CHG VDD
1M
DCHG VM VDD
GND 1
6.2V
1K
PIO
PIO 2
3
4
0.1F
VM
Cell
2.2K 0.025 PACK- RSENS 0.1F
GND
The circuit in Figure 2 depicts the DS2441 in a one-cell battery pack application. The circuit employs two p-channel power MOSFETs as charge and discharge protection switches along with a 1 M pullup resistor to PACK+ to turn off the charge FET. The DS2441 tracks current in and out of the pack by measuring the voltage across sense resistor RSENS (i.e., the voltage on ISENS with respect to GND). The 0.1 F capacitor and 2.2 k resistor on the ISENS pin form a low-pass filter to aid current measurement and accumulation. The diagram shows how the PIO pin can be used to drive an LED to implement a state-of-charge display. A zener diode limits the maximum voltage at the DQ terminal in the event that the pullup voltage is higher than the specified maximum DQ input voltage. Although the DS2441 has a 10kV ESD rating, this diode is recommended to clamp ESD events safely outside the IC. 3 of 29
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OVERVIEW
The DS2441 Block Diagram in Figure 1 shows the six major components of the DS2441: 1-Wire I/O port and 64-bit ROM ID Battery voltage A/D converter and monitor logic Battery current A/D converter and monitor logic Temperature sensor Registers and memory Control logic and outputs
POWER-ON RESET
The DS2441 executes a power-on reset (POR) whenever the voltages on both the VDD and DQ pins are below VPOR and then one or both voltages rise above VPOR. This includes the case where a lithium-ion cell is first attached to the DS2441 with DQ low or unconnected. During a POR, the DS2441 sets the POR bit in the Configuration Register to logic 0, locks Page 0 memory against accidental overwrite, and loads default values into the following registers from laser ROM: Control Register Delay Timing Register Discharge Termination Warning Register Manufacturing ID Register Configuration Register
Also during a POR, the DS2441 sets the Temperature, Voltage, and Current registers to their most negative values, as shown in Table 2. POR Register Values Table 2 Register Temperature Voltage Current Value decimal hex 80h -128 C 0 mV 0000h -5.12C FE00h
After reloading and resetting all of the registers mentioned above, the DS2441 enters its normal mode of operation, measuring voltage, current and temperature and reacting accordingly.
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LI-ION PROTECTION CIRCUITRY
During normal operation, the DS2441 constantly monitors cell voltage, current and temperature to protect the cell from overcharge (overvoltage), overdischarge (undervoltage), excessive charge and discharge currents (overcurrent), and thermal runaway (overtemperature). The DS2441 monitors for and protects against each of these conditions with separate circuitry in order to properly protect the lithium-ion cell from any single condition or combination of conditions that can arise. Conditions and DS2441 responses are described in the sections below and summarized in Table 3 and Figure 3.
LI-ION PROTECTION CONDITIONS AND DS2441 RESPONSES Table 3
Condition Name Overvoltage Undervoltage Activation Threshold Delay VCELL > VOV tOVD VCELL < VUV tUVD Response CHG off CHG off, DCHG high, Low Power Mode CHG off
DCHG high CHG off, DCHG high
Release Threshold VCELL < VCE exit Low Power Mode AND VCELL > VUV
Delay 0 0
Overcurrent, Charge Overcurrent, Discharge Overtemp
VISENS < -VOC VISENS > VOC VISENS > VSC TMEAS > TTRIP
tOCD tOCD tSCD 0
none none TMEAS < TTRIP - THYS
tREL tREL 0
(VCELL = VDD. TMEAS = measured temperature.) Overvoltage. If the voltage of the cell exceeds overvoltage threshold VOV for a period longer than overvoltage delay tOVD, the DS2441 shuts off the external charge FET and sets the overvoltage protection flag, OV, in the Status Register. When the cell voltage falls below charge enable threshold VCE, the DS2441 clears the OV flag and enables the charge FET (unless another protection condition prevents it). Except when a discharge protection condition also occurs, discharging remains enabled during overvoltage, with the discharge path consisting of the channel of the discharge FET and the body diode of the charge FET. Undervoltage. If the voltage on the cell drops below undervoltage threshold VUV for a period longer than undervoltage delay tUVD, the DS2441 shuts off the charge and discharge FETs, asserts the undervoltage protection flag, UV, in the Status Register and enters Low Power Mode to minimize the load it presents to the cell. See the section on Low Power Mode for more details. Overcurrent, Charge Direction. The voltage on the ISENS pin with respect to GND (VISENS) is the voltage across current sense resistor RSENS. If VISENS is less than -VOC (VOC is the overcurrent threshold) for a period longer than overcurrent delay tOCD, the DS2441 shuts off the external charge FET and sets the overcurrent protection flag, OC, in the Status Register. After the expiration of release delay tREL, the DS2441 clears the OC flag and enables the charge FET (unless another protection condition prevents it). If the overcurrent condition persists for tOCD after the charge FET is enabled, the DS2441 responds again. If the overcurrent condition persists indefinitely, the DS2441 cycles between protecting and releasing until an overvoltage condition arise. Except when a discharge protection condition also occurs, discharging remains enabled during charge-direction overcurrent, with the path consisting of the channel of the discharge FET and the body diode of the charge FET.
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Overcurrent, Discharge Direction. If VISENS is greater than overcurrent threshold VOC for a period longer than overcurrent delay tOCD, or if VISENS is greater than short circuit threshold VSC for a period longer than short circuit delay tSCD, the DS2441 shuts off the external discharge FET and sets the overcurrent protection flag, OC, in the Status Register. After the expiration of release delay tREL, the DS2441 clears the OC flag and enables the discharge FET (unless another protection condition prevents it). If the overcurrent condition persists for tOCD or tSCD after the discharge FET is enabled, the DS2441 responds again. If the condition persists indefinitely, the DS2441 cycles between protecting and releasing until an undervoltage condition arise. Except when a charge protection condition also occurs, charging remains enabled during discharge-direction overcurrent, with the path consisting of the channel of the charge FET and the body diode of the discharge FET. Overtemperature. If the temperature of the DS2441 exceeds TTRIP, the DS2441 immediately shuts off both the charge and discharge FETs and sets the overtemperature flag, OT, in the Status Register. After the temperature drops below TTRIP - THYS, the DS2441 clears the OT flag and enables the charge and discharge FETs (unless another protection condition prevents it). This feature provides a secondary safety back-up mechanism beyond overvoltage and overcurrent protection.
LITHIUM-ION PROTECTION CIRCUITRY EXAMPLE WAVEFORMS Figure 3
VCELL VOV VCE VUV discharge VISENS charge TMEAS tREL CHG tOVD tOVD tREL DCHG tSCD tOCD tOCD tREL tUVD THYS TTRIP VSC VOC 0 -VOC
VDD 0 VDD 0 active inactive
Low Power Mode
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Summary. All of the protection conditions described above are OR'ed together to affect the CHG and DCHG outputs. Taking the OV, UV and OT bits from the Status Register and considering the OC Status Register bit to be the logical OR of DOC (discharge overcurrent) and COC (charge overcurrent), the equations for CHG and DCHG are as follows:
DCHG = OT or DOC or UV or Low Power Mode CHG = OT or COC or OV or Low Power Mode
LOW POWER MODE
The DS2441 enters Low Power Mode when an undervoltage condition exists on the lithium-ion cell or when the host system sets the LPM bit in the Control Register. While in Low Power Mode, the DS2441 shuts off the external charge and discharge FETs and turns off most of its internal circuitry to reduce its load on the cell to IDD1 (1 A typical). The DS2441 stays in Low Power Mode until it is "awakened" by the attachment of a charger to the battery pack (voltage on CHG pin > VDD) or a high-to-low transition on the DQ pin. After either stimulus, the DS2441 powers up fully, makes initial measurements with the charge and discharge FETs off (to prevent charging until it can verify the cell is not overvoltage), and then returns to its normal mode of operation. Charging from Low Power Mode. Charging an undervoltage pack is as simple as applying a charger to the pack. The presence of the charger automatically triggers the DS2441 to leave Low Power Mode, make initial measurements with the FETs off, and return to its normal mode of operation. Generally the DS2441 starts normal operation with the discharge FET off (because the cell is still undervoltage) and the charge FET on, which allows charging to proceed. If the charger pulls the cell voltage above undervoltage threshold VUV before the expiration of undervoltage delay tUVD, the DS2441 remains in its normal mode of operation and charging can continue. If the cell remains below VUV for tUVD, the DS2441 shuts off the charge and discharge FETs, asserts the UV flag, and returns to Low Power Mode. Once back in Low Power Mode, the presence of the charger again triggers the DS2441 to go back to its normal mode of operation where charging can continue for at least tUVD. As long as the charger is applied to the pack, the DS2441 repeatedly cycles between its normal mode of operation (for tUVD) and Low Power Mode (for approximately 21 ms) until the cell has been charged above VUV. After the cell is above VUV, the DS2441 remains in its normal mode of operation and charging continues normally.
REFRESHING UNDERVOLTAGE PACKS
In the worst-case undervoltage situation, a battery can be so far discharged that VDD is outside the specified operating range of the DS2441, leaving the DS2441 without a power supply and unable to allow the charging necessary to correct the situation. The Refresh bit (RFSH) in the Control Register and the ability to parasitically steal power from the DQ pin are features that allow any DS2441-based battery pack to be refreshed from even the deepest undervoltage situation. Parasite Power. As is the case for many Dallas 1-Wire products, the DS2441 can, using an on-chip capacitor, parasitically steal enough power from the DQ line to support register and memory accesses even with no voltage present on the VDD pin. DQ must be pulled up to at least 3V, and maximum pulse width specifications must be met to ensure proper parasite-powered operation. Refresh Bit. Setting the RFSH bit in the Control Register to logic 1 causes the DS2441 to mask the effect of undervoltage on the CHG output, stay in the normal mode of operation (and out of Low Power Mode), and power all of its circuitry only from the DQ pin. Because all DS2441 circuitry is powered 7 of 29
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from DQ when this bit is set, DQ must subsequently remain high to support this mode of operation. A high-to-low transition on DQ clears the RFSH bit. Refreshing Undervoltage Packs. To charge severely undervoltage DS2441-based battery packs, apply a charger to the pack and read the Status Register to check the value of the UV bit. If UV=1, set the RFSH bit to logic 1 and pull DQ high to function as the DS2441' power supply. The DS2441 draws power s from DQ and allows charging to occur as long as DQ remains high and no charge protection condition arises. To periodically check whether the undervoltage condition remains, read the Status Register to check the value of UV. (The first high-to-low transition on DQ during the Status Register read will clear the RFSH bit. If the undervoltage condition remains, as soon as the RFSH bit is cleared the DS2441 will return to Low Power Mode, disabling charging.) If UV is still logic 1, set RFSH to logic 1 and pull DQ high to continue charging. Loop in this manner until UV=0. When UV is low, the DS2441 will be in its normal operating mode and will support normal charging.
CURRENT MEASUREMENT
The DS2441 measures current flow into and out of the battery pack by measuring the voltage across sense resistor RSENS connected between the PACK- terminal of the battery pack and the negative terminal of the battery. To accomplish this, the GND pin on the DS2441 is connected to the negative terminal of the battery and the ISENS pin is connected, through a low-pass filter, to the PACK- terminal of the pack. To measure current, the DS2441 actually measures VISENS with respect to GND. In its normal mode of operation, the DS2441 takes current measurements continuously with no assistance from the host system. In Low Power Mode, the DS2441 suspends current measurements. The DS2441 measures the voltage drop across RSENS using a digital sampling and accumulation scheme. The use of an external low-pass filter with a corner frequency below 2 kHz on the VISENS pin is recommended. The current is measured with a signed 11-bit (0.005C) resolution. The last completed measurement is placed in the Current Register using a sign-extended, two' s-complement format. This register is not updated while it is being read by the host system to ensure that only the last completed conversion is read out. The Current Register is scaled such that a count of 20010 corresponds to a current of 1C. Thus, the range of current flow that can be measured is from -5.115C (discharging) to +5.115C (charging). The sign (S) of the current measurement, indicating charge or discharge, resides in the six most significant bits of the Current Register, as shown in Figure 4. Some example Current Register values are shown in Table 4.
CURRENT REGISTER FORMAT Figure 4
27 msb S S 26 25 24 23 22 21 20 lsb 29 28 MSB LSB
(unit = 0.005C) S S S S
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CURRENT REGISTER EXAMPLE VALUES Table 4
Battery Current +5.115C +1.000C +0.100C +0.010C +0.005C 0C -0.005C -0.010C -0.100C -1.000C -5.115C Register Value Binary 0000 0011 1111 1111 0000 0000 1100 1000 0000 0000 0001 0100 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1111 1111 1110 1100 1111 1111 0011 1000 1111 1100 0000 0001 Hex 03 FF 00 C8 00 14 00 02 00 01 00 00 FF FF FF FE FF EC FE 38 FC 01
The value of current sense resistor RSENS should be selected to provide a 48.8 mV drop across it at a 1C rate. This value corresponds to 1 LSB = 244 V. Different voltage-to-current scaling factors can be used to accommodate a larger dynamic range, higher resolution, or less voltage loss at a given discharge current. Alternate scaling factors must be properly interpreted by the host system.
CURRENT ACCUMULATORS
The DS2441 maintains three different current accumulator registers. The Integrated Current Accumulator (ICA) facilitates battery gas gauging and remaining capacity reporting by tracking the net current flow into and out of the battery. The Charge Current Accumulator (CCA) and Discharge Current Accumulator (DCA) support battery end-of-life estimation by accumulating total charge current and discharge current respectively. Each completed current measurement increments or decrements the ICA and increments the CCA (if current is positive) or increments the DCA (if current is negative). Integrated Current Accumulator. The ICA is an 8-bit, read/write, up/down counter with 0.005C resolution that represents the amount of capacity remaining in the battery in terms of the full capacity (1C), normalized to a count of 20010. Thus, an ICA count of 20010 represents 1C of charge, 100% of capacity, or a fully charged battery. A count of 0 represents 0% of capacity, or a fully discharged battery. The ICA does count up to 25510, but does not roll over if incremented above an equivalent of 1.27C. Because batteries have an inherent charging inefficiency, the ICA may read higher than 200 (or 1C) after a full charge. Two methods are available for handling ICA values greater than 200: (1) reduce the ICA to 200 after a full charge, or (2) leave the ICA value alone and instead create a scaling factor of 200/ ICA for use by the host system. Figure 5 shows the format of the ICA register.
ICA REGISTER FORMAT Figure 5
27 msb 26 25 24 23 22 21 20 lsb
(unit = 0.005C)
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Charge and Discharge Current Accumulators. The Charge Current Accumulator (CCA) is a 16-bit, read/write, up-only counter with 0.16C resolution which accumulates the total charging current the battery pack has seen since the CCA was last reset. It is only updated when current through sense resistor RSENS is positive; i.e., when the battery is being charged. Similarly, the Discharge Current Accumulator (DCA) is a 16-bit, read/write, up-only counter with 0.16C resolution which accumulates the total discharging current the battery pack has seen since the DCA was last reset. Each counter is incremented at the rate of once per 0.16C, thus allowing six updates for each complete charge or discharge cycle. Figure 6 shows the format of the CCA and DCA registers.
CCA AND DCA REGISTER FORMAT Figure 6
27 msb 26 25 24 23 22 21 20 lsb 28 MSB LSB
(unit = 0.16C)
215 214 213 212 211 210 29
The ICA, CCA and DCA can be disabled by setting the ACC bit in the Configuration Register to logic 0. When the accumulators are disabled, bytes 0, 2, 3, 4 and 5 of Page 2 become general purpose memory available to the host system. Current Accumulator Threshold. In order to allow accumulator adjustments for offset versus resolution, two Configuration Register bits (TH1 and TH2) can be used to set a threshold on the measured current below which the ICA, CCA and DCA won' accumulate. When the threshold is set larger than t the maximum offset voltage of the internal A/D converter, the offset is effectively ignored by the accumulators. A higher threshold setting offers maximum granularity and is recommended for highcurrent use. A lower threshold setting is used to enhance long-term accuracy for light-duty battery use. Table 5 enumerates the available threshold settings.
CURRENT ACCUMULATOR THRESHOLD SETTINGS Table 5
TH2 0 0 1 1 TH1 0 1 0 1 Threshold None (default) 2 LSB 4 LSB 8 LSB
DISCHARGE TERMINATION WARNING
The DS2441 continuously compares the ICA value with the alarm threshold stored in the read/write Discharge Termination Warning (DTW) Register. If the ICA drops below the DTW threshold, the DS2441 sets the DTW flag in the Status Register to provide a low battery warning to the host system. The DTW flag is also set if the cell voltage falls below the discharge warning threshold VDW. The VDW voltage threshold provides a back-up warning in case extreme operating conditions cause ICA inaccuracy. The default DTW threshold value (0.000C) can be overwritten at any time. For a custom default value, consult the factory. The DTW Register has the same format as the ICA (see Figure 5).
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VOLTAGE MEASUREMENT
In its normal mode of operation, the DS2441 continuously measures the voltage of the cell. Voltage measurements are unsigned and have a 10-bit resolution. Each conversion cycle performs 32 consecutive voltage samples within 6.9ms (typical). If the AVG bit of the Configuration Register is set to logic 1 (default), the average value of the 32 samples is stored in the Voltage Register. If the AVG bit is set to logic 0, the minimum value of the 32 samples is stored. This is summarized in Table 6. In Low Power Mode, the DS2441 suspends voltage measurements.
VOLTAGE CONVERSION CONFIGURATION SETTINGS Table 6
AVG bit 1 0 Result Stored Average Minimum
The Voltage Register has the format shown in Figure 7.
VOLTAGE REGISTER FORMAT Figure 7
27 msb 0 0 26 25 24 23 22 21 20 lsb 29 28 MSB LSB
(unit=4.88 mV) 0 0 0 0
TEMPERATURE MEASUREMENT
In its normal mode of operation, the DS2441 continuously measures pack temperature. After each measurement, two' s-complement temperature information is stored in the 8-bit Temperature Register. The Temperature Register has the format shown in Figure 8. Some example Temperature Register values are shown in Table 7. In Low Power Mode, the DS2441 suspends temperature measurements.
TEMPERATURE REGISTER FORMAT Figure 8
S msb 26 25 24 23 22 21 20 lsb
(unit = 1 C)
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TEMPERATURE REGISTER EXAMPLE VALUES Table 7
Battery Temperature +85C +25C +2C +1C 0C - 1C - 2C - 25C - 40C Register Value Binary Hex 0101 0101 55 h 0001 1001 19 h 0000 0010 02 h 0000 0001 01 h 0000 0000 00 h 1111 1111 FF h 1111 1110 FE h 1110 0111 E7 h 1101 1000 D8 h
PROGRAMMABLE I/O
The programmable I/O port of the DS2441 allows for control and sensing of in-pack components such as speakers, vibration motors, FETs, LEDs and tamper control circuits. Using the Channel Access command with the R/ W Configuration Register bit set to logic 1 (read), the host system can monitor the state of the PIO pin by having the DS2441 translate logic 0s and logic 1s on the PIO pin into 1-Wire Read 0 and Read 1 timeslots on the DQ pin. Using the Channel Access command with R/ W set to logic 0 (write), the host system can control the PIO pin by having the DS2441 translate 1-Wire Write 0 and Write 1 timeslots on the DQ pin into logic 0s and logic 1s on the PIO pin. The DS2441 turns off the PIO output driver when it enters Low Power Mode or when a pack disconnection is sensed. See the Channel Access paragraph of the Function Command section and the Pack Disconnection section for more information.
PACK DISCONNECTION
The DS2441 can sense the disconnection of the battery pack from the host system. When the pack is separated from the host, the 1-Wire bus pullup resistor in the host is disconnected from the DQ pin of the DS2441. Once this pullup has been removed, a small current sink (<5 A) on the DQ pin pulls the DQ pin low. If the DQ pin remains low for more than 2 * tRSTL,MAX (approximately 2 ms) the DS2441 realizes that the extended low period represents a pack disconnection. When a pack disconnection is detected, the DS2441 turns off the PIO output driver. This circuit is turned off so that it doesn' drain the t cell during long disconnection periods. All other DS2441 circuitry remains active during pack disconnection.
64-BIT ROM ID
Each DS2441 contains a unique, factory-lasered ROM ID code that is 64 bits long. The first 8 bits of this ID are the 1-Wire family code (25h for DS2441). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (see Figure 9). The 64-bit ROM ID and the 1-Wire I/O circuitry built into the device allow the DS2441 to adhere to the 1-Wire protocol detailed in the 1-Wire Bus System section below.
ROM ID FORMAT Figure 9
8-bit CRC 48-bit Serial Number 8-Bit Family Code (25h)
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The ROM ID also aids in battery pack clone protection. The upper 12 bits of the 48-bit serial number within the ROM ID can be laser-programmed to indicate that a given DS2441 and the battery pack in which it resides belong to a particular manufacturer. Once reserved, a given pattern in this 12-bit field belongs exclusively to the company that requested it. That company can then create a software routine in their host systems to check for their specific pattern in the ROM ID each time a battery pack is attached to the host system. If the pack fails to produce a 64-bit ID with the proper pattern, it must be an unauthorized clone pack. The host system can then take appropriate action, such as refusing to operate from the clone pack or refusing to charge it.
CRC GENERATION
The DS2441 has an 8-bit CRC stored in the most significant byte of its 64-bit ROM ID. To ensure errorfree transmission of the ROM ID, the host system can compute a CRC value from the first 56 bits of the ROM ID and compare it to the CRC from the DS2441. The host system is responsible for verifying the CRC value and taking action as a result. The DS2441 does not compare CRC values and does not prevent a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC can result in a communication channel with a very high level of integrity. The 1-Wire CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as shown in Figure 10, or it can be generated in software. Additional information about the Dallas 1-Wire Cyclic Redundancy Check is available in Application Note 27 entitled "Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch Memory Products." In the circuit in Figure 10, the shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value.
1-WIRE CRC GENERATOR BLOCK DIAGRAM Figure 10
input msb XOR XOR lsb XOR
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MEMORY
The DS2441 contains four 32-byte pages of memory. See the page descriptions below, the Memory Map in Figure 11, and the detailed register descriptions on the pages that follow for more information. Locations labeled "Reserved" in the Memory Map always read out FFh. Locations labeled "unused" always read out 00h. Page 0 contains the Control, Delay Timing, Discharge Termination Warning, and Manufacturing ID registers. All of these registers are read/write except the read-only Manufacturing ID. This entire page can be locked against accidental write access by setting the LOCK bit of the Status Register to logic 1. During a power-on reset (POR) event, the DS2441 loads each of these registers with default values stored in laser ROM and set the Status Register LOCK bit. See the Discharge Termination Warning section and the sections on the Control, Delay Timing and Manufacturing ID registers for more details. Page 1 is read only and contains the Status Register, the Temperature Register and the Voltage Register. See the Temperature Measurement, Voltage Measurement and Status Register sections for more information. Page 2 contains the Configuration Register, the Current Register and the ICA, CCA and DCA. During a power-on reset event the DS2441 loads the Configuration Register with its default value stored in laser ROM. The ICA, CCA and DCA registers power-on in a random state and should be set to a known value by the host system. See the Current Measurement, Current Accumulators and Configuration Register sections for more details. Page 3 contains 32 bytes of user memory. All memory locations in this page power-on in a random state. Since the registers and memory in the DS2441 are full-CMOS SRAM, battery pack data is maintained by battery power even during undervoltage conditions. If the battery pack is externally short circuited, causing temporary battery voltage collapse, power circuitry in the DS2441 maintains acceptable voltage to the memory for at least tSCD to allow time for the lithium-ion protection circuitry to turn off the discharge FET and remove the cause of the supply voltage collapse. All registers and user memory in the DS2441 can be read and written under all power supply conditions, including loss of voltage on the VDD pin, via the parasite-powered 1-Wire bus.
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MEMORY MAP Figure 11/
Page 0 (lockable) Control Register Delay Timing Register Discharge Termination Warning Manufacturing ID Address 00 h 01 h 02 h 03 h 04 h 05 h 1F h Address 00 h 01 h 02 h 03 h 04 h 05 h 06 h 1F h Address 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 1F h Address 00 h 1F h Read/White R/W R/W R/W R
LSB MSB
Reserved Page 1 Status Register Temperature Register unused unused Voltage Register
R Read/White R R R R R
LSB MSB
Reserved Page 2 Integrated Current Accumulator Configuration Register Charge Current Accumulator Discharge Current Accumulator Current Register
R Read/Write R/W R/W R/W R/W R
LSB MSB LSB MSB LSB MSB
Reserved Page 3 User Byte 0 User Byte 31
R Read/Write R/W
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CONTROL REGISTER
The format of this register is shown in Figure 12. Bits 5 and 4 are read-only and return logic 0 when read. The function of each bit is described in detail in the paragraphs below.
CONTROL REGISTER FORMAT Figure 12
bit 7 bit 6 bit 5 0 bit 4 0 bit 3 bit 2 bit 1 bit 0
LPM RFSH
CHG DCHG CHE DCHE
LPM - Low Power Mode. Setting this bit to logic 1 puts the DS2441 into Low Power Mode. See the section on Low Power Mode for more details. The default value is 0 (inactive). RFSH - Refresh Mode. Setting this bit to logic 1 puts the DS2441 into Refresh Mode. See the section on Refreshing Undervoltage Packs for more information. A high-to-low transition on the DQ pin clears this bit to logic 0 and disables Refresh Mode.
CHG - State of CHG output pin. This read-only bit mirrors the state of the CHG output pin. DCHG - State of DCHG output pin. This read-only bit mirrors the state of the DCHG output pin.
CHE - Charge enable. Writing logic 0 to this bit disables charging ( CHG output driver off, external charge FET off) regardless of cell or pack conditions. Writing logic 1 to this bit enables charging, subject to override by the presence of any protection conditions. DCHE - Discharge enable. Writing logic 0 to this bit disables discharging ( DCHG output driver off, external discharge FET off) regardless of cell or pack conditions. Writing logic 1 to this bit enables discharging, subject to override by the presence of any protection conditions.
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DS2441
DELAY TIMING REGISTER
The Delay Timing Register provides a means to configure each of the protection delay times-- tREL, tOVD, tUVD, and tOCD-- to one of four values, allowing the DS2441 to be fine-tuned for its application environment. The format of the register is shown in Figure 13. The standard default value loaded from laser ROM during power-on reset is 00h. Contact the factory for a different default value. See the Lithium-Ion Protection section above for more details on these timing values.
DELAY TIMING REGISTER FORMAT Figure 13
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
REL
OVD
UVD
OCD
REL - tREL timing. This field indicates one of four settings for tREL, the length of time that charging and discharging are disabled following the detection of overcurrent conditions. See Table 8 for REL values and corresponding tREL timing. OVD - tOVD timing. This field indicates one of four settings for tOVD, the delay time during which the voltage of the cell must remain above overvoltage threshold VOV before charging is disabled due to an overvoltage condition. See Table 8 for OVD values and corresponding tOVD timing. UVD - tUVD timing. This field indicates one of four settings for tUVD, the delay time during which the voltage of the cell must remain below undervoltage threshold VUV before the DS2441 disables charging and discharging and enters Low Power Mode. See Table 9 for UVD values and corresponding tUVD timing. OCD - tOCD timing. This field indicates one of four settings for tOCD, the delay time during which pack current must be too high (VISENS > VOC for discharge or VISENS < -VOC for charge) before charging or discharging is disabled due to an overcurrent condition. See Table 10 for OCD values and corresponding tOCD timing.
REL AND OVD SETTINGS Table 8
REL, OVD 00 01 10 11 Min 384 768 1536 3072 tREL, tOVD (ms) Typ 512 1024 2048 4096 Max 640 1280 2560 5120
UVD SETTINGS Table 9
UVD 00 01 10 11 Min 24 48 96 192 tUVD (ms) Typ 32 64 128 256 17 of 29 Max 40 80 160 320
DS2441
OCD SETTINGS Table 10
OCD 00 01 10 11 Min 1.5 3 6 12 tOCD (ms) Typ 2 4 8 16 Max 2.5 5 10 20
STATUS REGISTER
The Status Register contains seven read-only status flags. Bit 7 of the register is read-only and always returns logic 0. The format of the register is shown in Figure 14. The various flags are described in the paragraphs below.
STATUS REGISTER FORMAT FIGURE 14
bit 7 0 bit 6 bit 5 bit 4 bit 3 OV bit 2 UV bit 1 OC bit 0 DTW
PIO LOCK OT
PIO - State of the PIO pin. This flag mirrors the logic state of the PIO pin, regardless of whether PIO is set up as an input or an output. The PIO flag is updated every time Page 1 of memory (the page containing the Status Register) is accessed by the host system. LOCK - Page 0 Lock. This flag indicates whether Page 0 is locked so that it cannot be written (LOCK=1) or unlocked for read/write access (LOCK=0). This bit is set and cleared by the execution of the Lock Register and Unlock Register commands. The power-on default value for this bit is logic 1 (locked). OT - Overtemperature. This bit indicates the presence (OT=1) or absence (OT=0) of an overtemperature protection condition. OV - Overvoltage. This bit indicates the presence (OV=1) or absence (OV=0) of an overvoltage protection condition. UV - Undervoltage. This bit indicates the presence (UV=1) or absence (UV=0) of an undervoltage protection condition. OC - Overcurrent. This bit indicates the presence (OC=1) or absence (OC=0) of an overcurrent protection condition. DTW - Discharge Termination Warning. This status bit is set to logic 1 when the Integrated Current Accumulator (ICA) value drops below the Discharge Termination Warning (DTW) threshold or cell voltage drops below discharge warning threshold VDW. This bit is reset to logic 0 when the ICA is higher than the DTW threshold and the voltage of the cell is above VDW.
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DS2441
CONFIGURATION REGISTER
The Configuration Register contains six read/write configuration bits. Bits 3 and 2 are read only and always return logic 1 when read. The format of the register is shown in Figure 15. The various bits are described in the paragraphs below.
CONFIGURATION REGISTER FORMAT Figure 15
bit 7 bit 6 bit 5 TH1 bit 4 bit 3 1 bit 2 1 bit 1 bit 0
ACC TH2
POR
R/W AVG
ACC - Accumulator enable. Setting this bit to a logic 0 disables the ICA, CCA and DCA functions, freeing up bytes 0, 2, 3, 4 and 5 in Page 2 for general purpose use. A logic 1 (power-on reset default) in this bit enables the accumulators. TH1, TH2 - Accumulator threshold bits. When the current accumulators are active, TH1 and TH2 select one of four accumulator threshold values. See Table 5 for possible threshold values.
POR - Power-on reset. A logic 0 in this bit indicates that a power-on reset has occurred. Writing a logic
1 resets this flag so that subsequent power-on reset events can be detected.
R/ W - PIO pin read/write direction bit. Setting this bit to a logic 1 configures the DS2441 to allow the
host system to read from the PIO pin using the Access Channel command. A logic 0 in this bit configures the device to allow the host system to write to the PIO pin using the Access Channel command. The power-on reset default value of this bit is logic 1 (read). AVG - Voltage A/D sampling method. This bit controls whether the average value (logic 1) or the minimum value (logic 0) of each 32-sample group is stored in the Voltage Register. The power-on reset default value is logic 1 (average).
THE MANUFACTURING ID
The value stored in this 16-bit read-only register can be laser-programmed by Dallas Semiconductor to provide pack customization. Fields in this register can encode information such as the pack manufacturer, assembly location and capacity. Unless a custom value is requested, the DS2441 ships with 0000h in this register. Contact the factory to request a custom Manufacturing ID value.
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DS2441
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. A multi-drop bus is a 1-Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the DS2441 is a slave device. The bus master is typically a microcontroller in the host system. The discussion of this bus system below consists of three topics: Hardware Configuration, Transaction Sequence, and 1-Wire Signaling.
HARDWARE CONFIGURATION
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the bus with open-drain or tri-state output drivers. The DS2441 uses an open-drain output driver as part of the bi-directional interface circuitry shown in Figure 16. If a bi-directional pin is not available on the bus master, separate output and input pins can be tied together. The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the value of this resistor should be approximately 5 k . The idle state for the 1-Wire bus is high. If, for any reason, a bus transaction must be suspended, the bus MUST be left in the idle state in order to properly resume the transaction later. If the bus is left low for more than 120 s, slave devices on the bus begin to interpret the low period as a Reset Pulse, effectively terminating the transaction.
1-WIRE BUS INTERFACE CIRCUITRY Figure 16
BUS MASTER +5V 4.7K RX 5 A Typ. RX = Receive TX = Transmit 100 OHM MOSFET RX DS2441 1-WIRE PORT
TX
TX
TRANSACTION SEQUENCE
The protocol for accessing the DS2441 via the 1-Wire port is as follows: Initialization ROM Command Function Command Transaction/Data
The sections that follow describes each of these step in detail.
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DS2441
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence consisting of a Reset Pulse transmitted by the bus master followed by a presence pulse simultaneously transmitted by the DS2441 and any other slaves on the bus. The presence pulse tells the bus master than one or more devices are on the bus and ready to operate. For more details, see the 1-Wire Signaling section below.
ROM COMMANDS
Once the bus master has detected the presence of one or more slaves, it can issue one of the four ROM Commands described below. The name of each ROM Command is followed by the eight-bit opcode for that command in square brackets. Figure 17 below presents a transaction flow chart of the four ROM Commands. Read ROM [33h]. This command allows the bus master to read the DS2441' 8-bit family code (25h), s unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). Match ROM [55h]. The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to specifically address one DS2441 on the 1-Wire bus. Only the DS2441 that exactly matches the 64-bit ROM sequence responds to the subsequent Function Command. All slaves that do not match the 64-bit ROM sequence wait for a reset pulse. This command can be used with one or more devices on the bus. Skip ROM [CCh]. This command saves time when there is only one DS2441 on the bus by allowing the bus master to issue a Function Command without specifying the 64-bit ID of the slave. If more than one slave device is present on the bus and the subsequent Function Command instructs the slaves to send data to the master, a data collision occurs when all slaves transmit data at the same time. Search ROM [F0h]. This command allows the bus master to use a process of elimination to identify the 64-bit ROM IDs of all slave devices on the bus. The ROM search process involves the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM ID. After one complete pass through all 64 bits, the bus master knows the ROM ID of one device. The remaining devices can then by identified on additional passes. See Chapter 5 of the Book of DS19xx iButtonTM Standards for a comprehensive discussion of a ROM search, including an actual example.
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DS2441
ROM COMMAND FLOW CHART Figure 17
MASTER Tx RESET PULSE
DS2441 Tx PRESENCE PULSE
MASTER Tx ROM FUNCTION COMMAND
33h READ ROM
NO
55h MATCH ROM
NO
F0h SEARCH ROM
NO
CCh SKIP ROM
NO
YES DS2441 Tx FAMILY CODE 1 BYTE
YES MASTER Tx BIT 0
YES DS2441 Tx BIT 0 DS2441 Tx BIT 0 MASTER TX BIT 0
YES MASTER Tx FUNCTION COMMAND
DS2441 Tx SERIAL NUMBER 6 BYTES BIT 0 MATCH ? DS2441 Tx CRC 1 BYTE NO NO BIT 0 MATCH ?
YES MASTER Tx BIT 1
YES DS2441 Tx BIT 1 DS2441 Tx BIT 1 MASTER TX BIT 1
BIT 1 MATCH ?
NO
NO
BIT 1 MATCH ?
YES
YES
MASTER Tx BIT 63
DS2441 Tx BIT 63 DS2441 Tx BIT 63 MASTER TX BIT 63
MASTER Tx FUNCTION COMMAND
YES
BIT 63 MATCH ?
NO
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DS2441
FUNCTION COMMANDS
After successfully completing one of the four ROM Commands, the bus master can access the features of the DS2441 with any of the six Function Commands described below. The name of each Function Command is followed by the eight-bit opcode for that command in square brackets. Lock Register [43h]. This command locks (disables write access to) Page 0 memory and sets the LOCK bit in the Status Register. Unlock Register [44h]. This command unlocks (enables write access to) Page 0 memory and clears the LOCK bit in the Status Register. Read Register [BEh, XX]. This command reads the contents of page XX, starting at address 00h within the page. Valid page numbers are 00h through 03h. The page number byte must be entered immediately following the command opcode. The least significant bit from address 00h is available to be read immediately after the most significant bit of the page number has been entered. Reading proceeds automatically from address 00h to address 1Fh in the page. If the bus master continues to read beyond address 1Fh, the DS2441 continuously outputs logic 1. Data transfer may be terminated with a Reset Pulse at any point. The bus master need not read out whole pages or even whole bytes. Write Register [4Eh, XX]. This command writes to page XX, starting at address 00h within the page. Valid page numbers are 00h, 02h and 03h (Page 1 is read-only). The page number byte must be entered immediately following the command opcode. Data to be written to address 00h must be entered immediately following the page number byte. The memory in the DS2441 is written a byte at a time, and data transfer may be terminated with a Reset Pulse at any byte boundary. Read-only bits and "Reserved" memory locations are not affected by the write operation. Incomplete bytes are not written. Recall Setup [B8h]. This command reloads the power-on default values for the Control, Delay Timing, Discharge Termination Warning, Manufacturing ID and Configuration registers. Channel Access [F5h]. This command directs the DQ bit stream to/from the PIO pin of the DS2441. If the R/ W bit in the Configuration Register is logic 1 when this command is entered, read cycles on the 1Wire bus return the state of the PIO pin. The state of the PIO pin can be read for any number of bus cycles. If the R/ W bit is set to logic 0 when this command is entered, write cycles on the 1-Wire bus are translated into equivalent logic levels on the PIO pin. If data is written to the PIO pin, a Write 0 time slot enables the PIO pin' open-drain output driver after delay tD0, while a Write 1 time slot disables the s output driver after tD1. A pullup resistor must be connected between the PIO pin and the VDD pin to achieve a logic 1 value on PIO. A Reset Pulse on the 1-Wire bus terminates the data stream. After a Channel Access write is terminated, the PIO pin latches and drives the last value written until a new Channel Access command is given. See Figure 18 for Channel Access write timing.
CHANNEL ACCESS COMMAND WRITE TIMING Figure 18
tSLOT 1-Wire Bus tD0 PIO 0 1 tD1 tSLOT 1 tRST latch PIO tSLOT
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DS2441
FUNCTION COMMANDS Table 11
Command Lock Register Unlock Register Read Register Description Disables write access to Page 0 Enables write access to Page 0 Reads data from Page XX (XX = 00 to 03) Writes data to Page XX (XX = 00, 02, 03) Recalls Control, Timing, DTW, Mfg. ID and Configuration register defaults Controls or senses PIO pin state Command Protocol 43h 44h Bus State After Command Protocol Idle Idle Bus Data none none
BEh, XX
Master RX
up to 32 bytes of register data up to 32 bytes of register data none
Write Register
4Eh, XX
Master Tx
Recall Setup
B8h
Idle
Channel Access
F5h
Master RX ( R/ W =1) Master TX ( R/ W =0)
unlimited reads or writes
I/0 SIGNALING
The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the DS2441 are: the initialization sequence (Reset Pulse followed by Presence Pulse), Write 0, Write 1, and Read Data. All of these types of signaling except the Presence Pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2441 is shown in Figure 19. A Presence Pulse following a Reset Pulse indicates the DS2441 is read to accept a ROM Command. The bus master transmits (TX) a Reset Pulse for tRSTL. The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ pin, the DS2441 waits for tPDH and then transmits the Presence Pulse for tPDL.
1-WIRE INITIALIZATION SEQUENCE (RESET PULSE AND PRESENCE PULSE) Figure 19
tRSTL tPDH VCC DQ GND
LINE TYPE LEGEND: Bus master active low Both bus master and DS2441 active low DS2441 active low Resistor pullup
tRSTH tPDL
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DS2441
WRITE TIME SLOTS
A write time slot is initiated when the bus master pulls the 1-Wire bus line from a logic high (inactive) level to a logic low level. There are two types of write time slots: Write 1 time slots and Write 0 time slots. All write time slots must be tSLOT (60 to 120 s) in duration with a 1s minimum recovery time, tREC, between cycles. The DS2441 samples the 1-Wire bus line between 15 and 60 s after the line falls. If the line is high when sampled, a Write 1 occurs. If the line is low when sampled, a Write 0 occurs (see Figure 20). For the bus master to generate a Write 1 time slot, the bus line must be pulled to a logic low level and then released, allowing the line to pull up to a logic high level within 15 s after the start of the write time slot. For the host to generate a Write 0 time slot, the bus line must be pulled to a logic low level and remain low for the duration of the write time slot.
READ TIME SLOTS
A read time slot is initiated when the bus master pulls the 1-Wire bus line from a logic high level to logic low level. The bus master must keep the bus line low for at least 1 s and then release it to allow the DS2441 to present valid data. The bus master can then sample the data tRDV (15 s) from the start of the read time slot. By the end of the read time slot, the DS2441 releases the bus line and allow it to be pulled high by the external pullup resistor. All read time slots must be tSLOT (60 to 120 s) in duration with a 1 s minimum recovery time, tREC, between cycles. See Figure 20 for more information.
1-WIRE WRITE AND READ TIME SLOTS Figure 20
WRITE 0 SLOT WRITE 1 SLOT
tSLOT tLOW0 tREC VCC DQ GND
MIN 15s DS2441 Sample Window TYP MAX 30s >1s 15s
tSLOT tLOW1
MIN
DS2441 Sample Window TYP MAX 30s
15s
15s
READ 0 SLOT
READ 1 SLOT
tSLOT tREC VCC DQ GND
Master Sample Window >1s
tSLOT
Master Sample Window
tRDV
LINE TYPE LEGEND: Bus master active low Both bus master and DS2441 active low
tRDV
DS2441 active low Resistor pullup
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DS2441
ABSOLUTE MAXIMUM RATINGS*
Voltage on CHG pin, Relative to Ground Voltage on any other pin, Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +18V -0.3V to +7V -40C to +85C -55C to +125C 260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage Data Pin SYMBOL VDD DQ CONDITION
(-40 to +85 2.4V VDD 5.5V) C C,
MIN 2.4 -0.3 TYP MAX 5.5 5.5 UNITS V V NOTES 1 1
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Logic High Input Logic Low Shutdown Current SYMBOL VIH VIL IDD1 CONDITION At DQ, PIO At DQ, PIO DQ=0V, Low Power Mode DQ=5.0V, normal operation VOUT=0.4V VDQ=0.4V Sink Source DQ
(-40 to +85 2.4V VDD 5.5V) C C;
MIN 2.0 -0.3 TYP MAX 0.5 1.5 UNITS V V A A mA mA mA 0.3 500 1.8V 2.65 2.70 2.75 k 6, 10 1 1 NOTES 1 1 2, 3
1.0
Active Current
IDD2
70
100
2, 4
Output Current
IPIO IDQ
CHG, DCHG
-4 -4 -1
5
Input Resistance Power-On Reset Voltage Discharge Warning Voltage
RI VPOR VDW
V
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DS2441
ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUITRY
PARAMETER SYMBOL Overvoltage Detect VOV Charge Enable VCE Undervoltage VUV Detect Overcurrent Detect VOC Short Circuit Detect VSC Overtemperature TTRIP Trip Point Overtemperature THYS Hysteresis Overvoltage Delay tOVD Undervoltage Delay Overcurrent Delay Short Circuit Delay Release Delay tUVD tOCD tSCD tREL CONDITION
(-40 to +85 2.4V VDD 5.5V) C C;
MIN 4.300 3.9 2.45 103 350 82 TYP 4.350 4.0 2.5 105 450 85 4 MAX 4.400 4.1 2.55 107 550 88 UNITS V V V mV mV C C 640 5120 40 320 2.5 20 100 640 5120 ms ms ms ms ms ms
s
NOTES 1, 9 1, 9 1, 9 1 1
OVD=00(min) OVD=11(max) UVD=00(min) UVD=11(max) OCD=00(min) OCD=11(max) REL=00(min) REL=11(max)
384 3072 24 192 1.5 12 384 3072
512 4096 32 256 2 16 30 512 4096
9 9 9
ms ms
9
ELECTRICAL CHARACTERISTICS: CURRENT ACCUMULATOR
PARAMETER Timer Accuracy SYMBOL tERR CONDITION At 25C, VDD=3.6V At ISENS
(-40 to +85 2.4V VDD 5.5V) C C;
MIN TYP 1 0.5 1 MAX 3 1 UNITS % % % NOTES
Conversion Error
IERR
8
ELECTRICAL CHARACTERISTICS: VOLTAGE CONVERTER
PARAMETER Sampling Period Conversion Time Conversion Error Conversion Cycle SYMBOL CONDITION tSH For 32 samples tVCONV Single conversion VERR tCYCL Cell Voltage and Temp
(-40 to +85 2.4V VDD 5.5V) C C;
MIN TYP 6.9 215 10 MAX UNITS ms s mV ms NOTES
50 14.4
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DS2441
ELECTRICAL CHARACTERISTICS: THERMOMETER
PARAMETER Conversion Time Thermometer Error SYMBOL tTCONV TERR CONDITION at 0 C
(-40 to +85 2.4V VDD 5.5V) C C;
MIN TYP 215 2 MAX 3 UNITS s C NOTES 7
ELECTRICAL CHARACTERISTICS: 1-WIRE INTERFACE
PARAMETER Time Slot Recovery Time Write 0 Low Time Write 1 Low Time Read Data Valid Reset Time High Reset Time Low Presence Detect High Presence Detect Low DQ Capacitance SYMBOL tSLOT tREC tLOW0 tLOW1 tRDV tRSTH tRSTL tPDH tPDL CDQ CONDITION
(-40 to +85 2.4V VDD 5.5V) C C;
MIN 60 1 60 1 480 480 15 60 TYP MAX 120 120 15 15 960 60 240 25 UNITS
s s s s s s s s s
NOTES
pF
ELECTRICAL CHARACTERISTICS: PROGRAMMABLE I/O
PARAMETER Logic 1 prop. delay Logic 0 prop. delay SYMBOL td1 td0 CONDITION
(-40 to +85 2.4V VDD 5.5V) C C;
MIN 15 TYP MAX 60 300 UNITS
s
NOTES
ns
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DS2441
NOTES
1. 2. 3. 4. 5. 6. 7. 8. 9. All voltages are referenced to GND. Shutdown and active currents specified for the range 0 to 70 C C. IDD1 specified with cell voltage at VUV. IDD2 specified with VDD = 5.0V.
CHG is open drain and does not source current.
Input load is to GND. Maximum error values are guaranteed by design over the full temperature range. Current measurement accuracy is 2 LSB or 1%, whichever is greater. Contact the factory for different voltage trip points and default delay periods.
10. This input resistance is not present when the DS2441 is in Refresh Mode and the DQ pin is serving as a power supply input.
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